Large area, lateral GaN transistors for high voltage/high current operation, such as GaN power switches comprising GaN E-HEMTs, may comprise a plurality of transistor elements connected in parallel. For example, the topology of a large area, large gate width GaN E-HEMT may comprise a plurality of transistor elements in the form of islands which are interconnected in parallel. Each island comprises individual source, drain and gate electrodes and a plurality of islands are interconnected to form a multi-island transistor. Various topologies are known for large area transistors. Examples having an overlying interconnect structure comprising a source bus, a drain bus and a gate bus, which interconnect respective source, drain and gate electrodes of each island, are described in the Applicant's earlier filed patent applications.
For example, U.S. patent application Ser. No. 14/568,507, filed Dec. 12, 2014, now U.S. Pat. No. 9,153,509, entitled “Fault Tolerant Design for Large Area Nitride Semiconductor Devices” discloses a large area lateral transistor comprising a two-dimensional array a plurality of islands or cells, e.g. arranged as rows and columns. Each island comprises a source electrode, drain electrode and gate electrode. For each group or set of islands, e.g. a column of islands, source electrodes of individual islands are connected in parallel by a source strap (source bus); drain electrodes of individual islands are interconnected in parallel by a drain strap (drain bus); and gate electrodes of individual islands are interconnected by a gate strap (gate bus) to provide a transistor with a very large gate width, Wg.
Examples of other device topologies, interconnect arrangements and packaging solutions for lateral GaN power transistors are disclosed in:
U.S. patent application Ser. No. 15/091,867, filed Apr. 6, 2016, now U.S. Pat. No. 9,660,639, entitled “Distributed Driver Circuitry integrated with GaN Power Transistors”;
U.S. patent application Ser. No. 15/027,012, filed Apr. 15, 2015, now U.S. Pat. No. 9,659,854, entitled “Embedded Packaging for Devices and Systems Comprising Lateral GaN Power Transistors”;
U.S. patent application Ser. No. 15/064,750, filed Mar. 9, 2016, now U.S. Pat. No. 9,589,868, entitled “Packaging Solutions for Devices and Systems Comprising Lateral GaN Power Transistors”;
U.S. patent application Ser. No. 15/064,955, filed Mar. 9, 2016, now U.S. Pat. No. 9,589,869, entitled “Packaging Solutions for Devices and Systems Comprising Lateral GaN Power Transistors”;
U.S. patent application Ser. No. 14/681,676, filed Apr. 8, 2015, now U.S. Pat. No. 9,508,797, entitled “Gallium Nitride Power Devices using Island Topography”;
U.S. Pat. No. 1,020,712, filed Feb. 3, 2011, now U.S. Pat. No. 9,029,866, entitled “Gallium Nitride Power Devices using Island Topography”;
U.S. patent application Ser. No. 13/641,003, filed Apr. 13, 2011, now U.S. Pat. No. 8,791,508 entitled “High Density Gallium Nitride Devices using Island Topology”; and
U.S. patent application Ser. No. 13/388,694, filed Aug. 4, 2010, now U.S. Pat. No. 9,064,947 entitled “Island Matrixed Gallium Nitride Microwave and Power Switching Transistors”.
All these patents and applications are incorporated herein by reference in their entirety.
In large area GaN transistors, for example, a device having an area of ˜1 cm2 or more, i.e. a die size of about 10 mm×10 mm, the length of on-chip wiring or interconnect tracks extending between the gate driver circuitry and gate electrodes of a large area GaN transistor can introduce significant parasitic on-chip inductances. Unbalanced gate inductances may lead to unbalanced and unstable operation, and hence, poor performance.
For example, as discussed in the above referenced U.S. Pat. No. 9,660,639, entitled “Distributed Driver Circuitry Integrated with GaN Power Transistors”, a large area GaN transistor may be partitioned into sections, and each section is interconnected to the gate driver circuit by differing lengths of source and gate interconnections. This arrangement introduces different amounts of parasitic inductance, i.e. inductances dependent on the lengths of on-chip wiring or interconnect. For high speed switching, it is desirable to have coherent synchronous turn-on/turn-off across all transistor sections of a large area multi-section GaN transistor.
Another consideration is that, when multiple GaN transistors are interconnected, or when multiple GaN transistor elements or sections of large area devices are connected in parallel, they are prone to current imbalance due to differences in parasitic resistances/inductances resulting from differing lengths of interconnect metallization for the gate drive signals.
GaN transistors are positive temperature coefficient (PTC) elements, and are self-heating during conduction. GaN transistors connected in parallel balance their currents during conduction time due to self-heating. Current imbalance is likely to occur during the turn-on rise time of switching transistors, due to lack of resistance balance. Parallel transistor cells on the same substrate balance their resistances during steady state operation. However, on a cold start, during turn-on, the resistances of different transistor cells are not the same, due to fabrication imperfections in large scale GaN transistors. Therefore, it is necessary to use a different mechanism to ensure that the transistor cells share their current during their rise time period.
One way to minimize the overall current imbalance regime is to minimize rise time, and particularly the gate plateau regime, by reducing gate resistance. However, reducing gate resistance adds to transistor gain and increases the likelihood of oscillations at the gate pin. Increasing gate resistance adds to switching losses and reduces the efficiency of the transistor.
Alternative solutions are needed to protect large scale and high current lateral GaN power transistors against potential damage associated with rise time current imbalances and differing delays during the turn-on state.